An integrated circuit is a microelectronic semiconductor device consisting of many interconnected transistors and other components. A single integrated circuit may comprise as few as one to two components, referred to as small-scaled integration (SSI), to as many as a thousand or more components, referred to as very-large-scaled integration (VLSI). Integrated circuits are typically fabricated on a wafer formed out of a suitable material such as silicon. On a single wafer, there may be 50 to 100 integrated circuits. Once fabricated, the wafer is cut into small rectangular dies comprising the individual integrated circuits. Each die is then packaged in a manner to protect the integrated circuit thereon.
For a variety of reasons, a certain percentage of the integrated circuits manufactured on a wafer will have manufacturing defects rendering the integrated circuits useless unless the circuits can be repaired. Such manufacturing defects may be attributed to material imperfections, technician error, or even the presence of a foreign object such as dust or dirt. Regardless of the cause of the defect, it is imperative that the defect be detected as early as possible in the final assembly process in order to preserve quality standards and to prevent any cost associated with the further processing of a defective product. Consequently, several tests are usually performed on an integrated circuit prior to the cutting of the wafer so that defective integrated circuits can be identified and repaired, if possible, before final assembly.
An important aspect of the testing performed on integrated circuits is that certain defects in the circuit are repairable if found prior to the packaging of the integrated circuit. For example, memory banks are typically designed to include redundant memory elements that may be mapped into and out of the circuit in order to replace defective memory elements. The defective memory elements are likewise mapped out of the memory bank so as to be rendered nonconsequential. The mapping in and mapping out of memory elements is typically done with a plurality of programmable fuse circuits that are configured to provide a control logic signal to a fuse logic circuit connected to the memory bank so as to program the operation of the memory bank by mapping in and mapping out elements. With reference to FIG. 1, a conventional programmable fuse circuit 12 utilized in programming memory is illustrated. In the fuse circuit 12, a fuse 14 is connected in series between ground (GND) and a load device 16. The load device 16 is also connected in series with a voltage supply (VDD). The resulting voltage divider is used to produce a logic output level that is dependent upon the state of the fuse. For instance, if the fuse is blown, the logical output level is high. Alternatively, if the fuse is not blown, the logical output level is low. Therefore, the programmable fuse circuit can be used to permanently program the operation of the memory bank.
One type of testing performed on integrated circuits during fabrication is functional logic testing. In functional logic testing, a stimulus in the form of a test pattern is applied to the input of an integrated circuit. The output of the integrated circuit is then observed and compared to a desired response pattern which would be expected if the integrated circuit is functioning properly. Preferably, numerous patterns are engineered and applied to the integrated circuit in order to thoroughly test the operation of the integrated circuit. Similarly, functional logic testing can be used to perform timing test by toggling the input signal to an integrated circuit in order to determine whether the integrated circuit meets the performance requirements for setup times, hold times, and propagation delays.
While functional logic testing is suitable for testing most integrated circuits, it is recognized that with complicated integrated circuits, particularly sub-circuits thereof, it may be difficult to stimulate the circuit with an input pattern and/or difficult to observe a response pattern which finds the fault. The sub-circuits may also be so deeply buried in multiple layers of surrounding circuitry that it is virtually impossible to physically access, much less apply the test pattern and/or observe an appropriate response pattern. Moreover, complicated integrated circuits such as application specific integrated circuits (ASIC's) are non-regular, and therefore, it is often impractical to engineer the large number of test patterns required to adequately test the ASIC in order to find all the combinations of faults and defects possible.
Another type of testing performed on integrated circuits is static current testing. In static current testing, the current drawn by an integrated circuit under test is measured when in the circuit is in a quiescent state. If a defect exists in the integrated circuit, a higher than normal static current (also referred to as quiescent current) flow is detected due to current paths caused by the defect. An advantage of this testing technique is that the current is observed through the power and ground connections of the integrated circuit which are accessible and easy to observe. In addition, this technique does not rely on the functional output of the integrated circuit or any sub-circuit thereof. Presently, static current testing is limited primarily to testing complimentary metal-oxide semiconductor (CMOS) circuits. This is because CMOS circuitry produces essentially no current while in a quiescent state. Therefore, if a current above a predetermined threshold is detected when the circuit is in a quiescent state, then a defect exists within the circuit.
However, a disadvantage of static current testing is that many types of integrated circuits are not characterized by having essentially no current flow while in a quiescent state as is the case with CMOS circuits. For example, the programmable fuse circuit 12 (FIG. 1) has a continuous static (i.e., quiescent) current path unless the fuse 14 is blown. Consequently, any integrated circuit incorporating the programmable fuse circuit 12 is not static current testable. This is a significant disadvantage since programmable fuse circuits like the one illustrated in FIG. 1 are commonly used in conjunction with fuse logic circuitry for permanently programming the operations of memory banks comprising random access memory (RAM), erasable programmable read only memory (EPROM), flash EPROM and numerous other suitable memory configurations, as discussed above.
In addition to the aforementioned needs in the industry, it has recently become desirable to have a unique machine readable serial number applied to integrated circuits for identification purposes. By providing a unique serial number on an integrated circuit, a variety of functions can be served. For instance, a data base of information regarding the origination, sale, specifications, etc. of an integrated circuit can be maintained. A plurality of programmable fuse circuits such as the one illustrated in FIG. 1 have been used to provide a binary serial number created by selectively blowing the fuses of respective fuse circuits. However, this method is undesirable because the programmable fuse circuits used for the serial number would be a constant power drain which is a critical design concern in most integrated circuit applications.
Thus, a heretofore need existed in the industry for a programmable fuse circuit with a static current path that can be selectively disabled.